Definition of Ecom Success & Failure Bit

[sgsims]

What causes the Success Bit to go High in an IB-741 (WX)?

[Greg]

This Success bit is SET ON if, after executing the WX inside the IBox, the SlotBusy bit comes back as OFF (meaning the ECOM100 is no longer busy) and the SlotError bit comes back as OFF (meaning the ECOM100 did not get an error).

The pseudo-code inside the IBox looks like this:

STR %P2.*2
ANDN %ECOM.SlotBusy
ANDN %ECOM.SlotError
OUT B7710.1
SET %P7

where:
%P2.*2 is Bit #2 of the Workspace Register used to indicate "Wait for Done" state (our definition).
%ECOM.SlotBusy is the SP bit of the ECOM100's slot.
%ECOM.SlotError is the SP bit of the ECOM100's slot.
%P7 is the Success Bit itself.

[sgsims]

Thanks Greg,

Once the Success bit goes High or (SET) what takes the success bit Low or (RST)?

[MikeS]

both the success and error bits are set OFF at the beginning of the instruction. one of them is guaranteed to come ON when the instruction ends.

[sgsims]

Thanks Mike,

How does the token passing affect the re-setting of the Success and failure bits?  I am testing those bits with two IB-740 & one IB-741 boxes on the same rung with an sp1 bit so that rung is scanned on every scan.

It looks like to me that the success bit is being reset the scan right after it is set.  I was expecting to see two of the three success bits on at any given time due to the fact that the success bit gets reset at the beginning of the instruction.  What I am seeing is only one success bit on at a time.

In other words what I expected was the first I-BOX success bit to be SET then the next I-Box Success bit gets SET,  then the third success BIT gets SET.  Then when the token goes back around to the first I-Box it would reset then set again on a later scan.

[franji1]

Since these instructions are NOT edge triggered, and since you have SP1 driving them, they will turn OFF on the scan IMMEDIATELY AFTER they turned ON (i.e. immediately after they completed), because you have told it to execute immediately (or technically, you have just told it to execute; "immediate" is dependent on the availability of the "token"), because it is power-flow enabled instruction, not an edge-triggered instruction.

TOKEN PASSING is responsible for handling the situations to get everybody to play nice.  Just because the first instruction says "I want the token NOW, immediately after the scan I gave up the token", it will NOT get the token if someone below him or above him got the token.  So "Enabling" and "Getting the token" are two different states, although those two state transitions CAN occur in the same scan if someone else did NOT already have the token.

[franji1]

Attached is a state transition diagram of the behavior of the ECRX/ECWX IBox instructions.

From the HOME state, if Enable(powerflow) is ON, it clears the Success and Error bits.  So SP1 driving your IBox will cause the Error/Success bits to be ON for 1 scan, regardless of how many other IBoxes or how slow the IBoxes are.

It then tries to get the ECOM100 RX/WX token from the ECOM100 IBox.

Then it ensures that the backplane SP busy bit is off (just in case you are doing native RX/WX in the same slot - BAD FORM - DO NOT MIX ECRX/ECWX with native RX/WX on the ECOM100 slot!!! The IBox won't "step on" your native RX/WX, but your native RX/WX could "hang" the EC* IBoxes indefinitely).

[franji1]

FYI, the first 3 states could occur within the same PLC scan (they are coded in that order in the expanded IBox logic).

[sgsims]

Thanks Franji,

You guys at Host are always spot on with your information!  I just have one more question regarding your chart.  In the state when the Success Bit is SET and the Token is releases how does the I_BOX instruction know to wait an additional scan before RESETING the SUCCESS BIT.  I know I'mm being picky put I am curious.  Best I can tell there is some logic that says only reset the SUCCESS or ERROR bit if it has been HIGH for one scan.

[franji1]

Thanks Franji,

You guys at Host are always spot on with your information!  I just have one more question regarding your chart.  In the state when the Success Bit is SET and the Token is releases how does the I_BOX instruction know to wait an additional scan before RESETING the SUCCESS BIT.  I know I'mm being picky put I am curious.  Best I can tell there is some logic that says only reset the SUCCESS or ERROR bit if it has been HIGH for one scan.

The IBox logic is just a macro.  Here is the "templatized" code for ECWX.  The magic is that the rungs for determining the DONE state must be BEFORE the rung that performs the actual native WX instruction.  This guarantees that the Success and Error bits will be ON for AT LEAST one scan.  See RUNGS 5/6 are the "check for completion" rungs (success/error completions), RUNG 7 is the WX rung (where the actual WX occurs), rung 8/9 are other "completion" rungs, rung 10 is power-flow restoration, so that the power flow ENTERING rung 1 is restored at the end (to make it LOOK LIKE an ATOMIC instruction, vs. 10 individual rungs with their own powerflow states, etc.!!!)

Code: [Select]

// ECWX (ECOM Write Network)
// P1 - ECOM#
// P2 - Workspace Register
// P3 - Slave ID
// P4 - "From" Master Element
// P5 - Number of Bytes
// P4 - "To" Slave Destination Element
// P7 - Success Bit
// P8 - Error Bit

// Workspace Bits reflect the STATE - at most 1 bit should be ON in the Workspace register (values 0, 1, 2, 4)
// P2 == K0 (no bits) - Home
// P2.*0 - WaitForRXWXToken
// P2.*1 - WaitForRXWXNotBusy
// P2.*2 - WaitForDone

// TEMPs
// B7710.0 - power flow upon entering IBox
// B7710.1 - when in WaitForDone state and Slot NOT Busy nor Slot Error at Top of Scan (success)
// B7710.2 - when in WaitForDone state and Slot Error at Top of Scan (error)
// B7710.3 - power flow when WX is executed but the SlotBusy SP bit does NOT come on (wrong slot)

// LOGIC STARTS HERE

// LAST HALF OF RUNG 1 (this is appended to the logic at the point of the IBox instruction)
// Save off Enable state into TEMP BIT
OUT B7710.0

// RUNG 2
// On First Scan, reset state machine to HOME state (Workspace = K0)
// Cannot reset success/error bits on first scan due to E471 Duplicate Coil error
// Do not allow anything else to occur on first scan
STR SP0
LD K0
OUT %P2

// RUNG 3
// If at Home state and have power flow, then clear the error and success bits and go to WaitForRXWXToken state
STRE %P2 K0
AND B7710.0
RST %P7
RST %P8
SET %P2.*0

// RUNG 4
// If at WaitForRXWXToken state and not on first scan and RX/WX Token is available,
// then get the RX/WX Token and go to WaitForRXWXNotBusy
STR %P2.*0
ANDN SP0
ANDN %ECOM.RXWXTokenInUse
SET %ECOM.RXWXTokenInUse
SET %P2.*1
RST %P2.*0

// RUNG 5
// This completion logic must be BEFORE the WX rung, otherwise it appears to be
// done IMMEDIATELY!  Duh!
//
// Top of Scan Status:
// --------------+----------------+-----------------------------------------------
// ECOM.SlotBusy | ECOM.SlotError | Result
// --------------+----------------+-----------------------------------------------
//   0-not busy  |   0-no error   | DONE, SUCCESS
// --------------+----------------+-----------------------------------------------
//   0-not busy  |   1-error      | Done, Error
// --------------+----------------+-----------------------------------------------
//   1-busy      |   0-no error   | not done, keep waiting
// --------------+----------------+-----------------------------------------------
//   1-busy      |   1-error      | not done, but error - REPORT AS DONE, W/ERROR
// --------------+----------------+-----------------------------------------------
//
// When we are in the WaitForDone state, if the slot is flagged as busy from the top of scan,
// and there are no slot errors at the top of scan, stay in this state (no logic for this).
// Otherwise, we are moving to the Home state as success or failure:
// Success:
//   STATE == WaitForDone AND ECOM.SlotBusy is FALSE AND ECOM.SlotError is FALSE; B7710.1 will be on
//   iff when this is true, set the Success bit
// Failure:
//   STATE == Wait AND AND ECOM.SlotError is TRUE; B7710.2 will be on iff when this is true,
//   set the Error bit (actually, this must be done as common logic towards end of logic)
// Common logic for transitioning to Home state is at end
STR %P2.*2
ANDN %ECOM.SlotBusy
ANDN %ECOM.SlotError
OUT B7710.1
SET %P7

// RUNG 6
STR %P2.*2
AND %ECOM.SlotError
OUT B7710.2

// RUNG 7
// Do the WX when the port is not busy.
// If the STATE == WaitForRXWXNotBusy and the Slot SP is NOT busy, then do the WX.
// Set the STATE variable to WaitForDone.
STR %P2.*1
ANDN %SPSlotBusy
LD %ECOM.Slot_MSByte
ORD %P3    // slave ID
LD %P5     // number of bytes
LDA %P4.o  // master source address in V memory
WX %P6     // slave destination address
SET %P2.*2
RST %P2.*1
ANDN %SPSlotBusy  // if the SlotBusy SP is OFF, then we are WXing to an EMPTY slot!
OUT B7710.3

// RUNG 8
// Common ERROR logic - when WX completed in error or when tried to WX to an empty slot
STR B7710.2
OR B7710.3
SET %P8

// RUNG 9
// Common DONE logic - set state to Home (K0), give up RX/WX Token
// Do this when WX completed successfully, when WX completed in error, or when tried to
// WX to an empty slot
STR B7710.1
OR B7710.2
OR B7710.3
LD K0
OUT %P2
RST %ECOM.RXWXTokenInUse

// FIRST HALF OF RUNG 10
// restore original power flow
STR B7710.0
OUT B7710.0  // this eliminates the E464 errors by having a complete rung


[sgsims]

Ok Franji..that was very helpful...I by no means understood all of that Macro code but I think I now understand how the Success and Error Bits are set and reset based on whether the RX/WX instruction is Edge triggered or SP1 driven.

One more last question...I promise.  The answer to this is probably staring me in the face in your Macro code but here is the question nonetheless.

If one edge triggers an I-Box RX/WX instruction then takes that edge trigger low on the next scan will that instruction complete along with the Setting of the Success or Error bits even though the instruction only had powerflow for one scan?

[franji1]

Ok Franji..that was very helpful...I by no means understood all of that Macro code but I think I now understand how the Success and Error Bits are set and reset based on whether the RX/WX instruction is Edge triggered or SP1 driven.

One more last question...I promise.  The answer to this is probably staring me in the face in your Macro code but here is the question nonetheless.

If one edge triggers an I-Box RX/WX instruction then takes that edge trigger low on the next scan will that instruction complete along with the Setting of the Success or Error bits even though the instruction only had powerflow for one scan?

Yes.  When you are in the HOME state, all it takes is POWERFLOW ON, and that ARMS the instruction (you move away from the HOME state, on to the RX/WX Token state).  The IBox COMPLETELY IGNORES powerflow for the remaining states.

To answer your next question  , it will NOT QUEUE requests (if you toggle it 5 times during the "busy" or non-HOME states), it will still only execute ONCE.  This is where STAGE sequencing is REALLY helpful in the case where you want to make these be EVENT-BASED reads/writes (vs. polling continuously).

[sgsims]

Great information!  I'll study your answers a bit.

Thanks again!