DMD 1.2.1 bug

[plcnut]

Gentlemen,

Leave it to me to break it   

I have attached 3 screenshots of a sample program.
The first shows 2 rungs with a series of 6 bits being set and reset on the output column.
The second shows where I have merged the rungs and re-drew them.
The third shows that the rung has been re-ordered after I Accepted them.
I understand the top section being moved down because of the AND above a JOIN. But, the other two bits (C5 and C6) have been reversed.
In this example it is no big deal, but when you do a rung with lots of outputs and an EXIT at the bottom, then this doesn't work so well.

[franji1]

Sadly, that is the nature of the stack based architecture (all Texas Instrument controllers, Koyo DL controllers, and Do-more).  It does not follow true power flow (never has).  Ladder Logic gets reduced to a binary expression tree, then to an RPN-line language (STR, AND, OR)

So the parallel rung in the middle screen shot becomes

STR C2 (PUSH C2 value on to the boolean stack)
SET C5 (take top of stack, if it is ON, turn ON C5 - no change to stack state)
RST C6 (take top of stack, if it is ON, turn OFF C6 - no change to stack state)
AND C1 (AND top of stack with C1 value)
SET C3 (take top of stack, if it is ON, turn ON C3 - no change to stack state)
RST C4 (take top of stack, if it is ON, turn OFF C4)

The ladder is ALWAYS "optimized" back to the "reverse generation" of the mnemonics (this is why you don't end up with dangling wires or extra space between contacts or between contact region and coil region - contact logic is optimized/justified to the top and to the left, coils are optimized/justified to go to the right and down the right power rail, NOT based off the CAD diagram of the wire drawing).  Some PLCs do it that way and follow a strict power-flow, ladder logic flow behavior.  Do-more does not.

(note that the boolean co-processor nor the Do-more PLC knows what a "ladder rung" is - that is completely fabricated by Designer; it just knows STR/AND/OR etc.  Hence, the boolean stack is 32 deep, but circular - it never "resolves" back to a stack depth of 0 because the OUT/SET/RST coils NEVER POP the boolean stack; the MATH stack however - that's completely different architecture).

[plcnut]

So the parallel rung in the middle screen shot becomes

STR C2 (PUSH C2 value on to the boolean stack)
SET C5 (take top of stack, if it is ON, turn ON C5 - no change to stack state)
RST C6 (take top of stack, if it is ON, turn OFF C6 - no change to stack state)
AND C1 (AND top of stack with C1 value)
SET C3 (take top of stack, if it is ON, turn ON C3 - no change to stack state)
RST C4 (take top of stack, if it is ON, turn OFF C4)

Mark, that is exactly what I would expect. But if you look at the rung it reordered it like this:

STR C2 (PUSH C2 value on to the boolean stack)
RST C6 (take top of stack, if it is ON, turn OFF C6 - no change to stack state)
SET C5 (take top of stack, if it is ON, turn ON C5 - no change to stack state)
AND C1 (AND top of stack with C1 value)
SET C3 (take top of stack, if it is ON, turn ON C3 - no change to stack state)
RST C4 (take top of stack, if it is ON, turn OFF C4)

Notice how it swapped the two outputs I highlighted.

[franji1]

NOW I see (sorry).  It not just swapped the "AND" branch, it swapped the COILs within (just) the AND branch.

That's an issue.  I'll look at it.

[franji1]

NOW I see (sorry).  It not just swapped the "AND" branch, it swapped the COILs within (just) the AND branch.

That's an issue.  I'll look at it.

Sorry, within the NON-AND branch