SET's and OUT's in stages

[plcnut]

Can someone please explain this for me. I'm running low on sleep so I might be missing something.

Open the attached program and load it in the simulator, when C1 is turned on it will reset itself and run the program through one loop. I would expect C0 and Y0 to be on when it is done, but it is not. I placed an INC at the end to confirm it is going through the loop.
Thanks

[b_carlton]

Remember that, once you JMP from a Stage, one final pass is made on the next scan to turn off any outputs which are the object of an OUT. The 'turnoff' scan of S1 will be doing that nullifying the effect of S2.

As a test in S2 add a second rung copying the state of Y0 and C0, by means of a SET, to another pair of memory spots. E.g. RST C2, C3, STR Y0, Set C2, Str C0, Set C3

Edit - I added the RSTs of C2 and C3 to the end of S2's first rung. The two conditional SETs were one rung each.

[BobO]

Mr. Nut...you love to color outside the lines don't you?

Bernie is right. Stages manage OUTs, and a handful of other instructions with specific behaviors, using 'termination' code that runs of the following scan. The task behavior you found before was actually due to the termination code not running in the specific case you identified.

Generally you would not want to mix SET/RST and OUT instructions in a Stage program for exactly this reason. And it is reasons like this that some people find Stage confusing. While very powerful, there are a few caveats.

[plcnut]

Thanks. I figured it had something to do with out's and termination.