News:

  • June 28, 2026, 06:27:18 PM

Login with username, password and session length

Author Topic: Stage Logic  (Read 7676 times)

JeffS

  • Hero Member
  • *****
  • Posts: 113
Stage Logic
« on: June 20, 2024, 06:11:33 PM »
Is there any reason I couldn't have a program that runs every scan, and within that program are a series of stages that I jump through, and do this every scan?

franji1

  • Bit Weenie
  • Host Moderator
  • Hero Member
  • *****
  • Posts: 3827
    • Host Engineering
Re: Stage Logic
« Reply #1 on: June 21, 2024, 09:54:27 AM »
That is what it does by default.  It always iterates through all the stages.  If they are disabled, they are skipped (CPU program pointer advances to the next stage in the program block - the program pointer is always trying to move forward to execute all logic and get to the bottom of the code block).

If you have any kind of looping/yielding instructions FOR/NEXT, WHILE, etc., those COULD affect whether stages are looked at every scan (but this is rare).

You can do a flow chart using Stage, if that's what your actual question is (what are you trying to solve?)

JeffS

  • Hero Member
  • *****
  • Posts: 113
Re: Stage Logic
« Reply #2 on: June 21, 2024, 10:27:26 AM »
So what I have is this very setup, but all stages that get toggled on, then off (via JMP) don't turn on the very next scan.  They only turn back on every other scan.

Attached is a sample program that demonstrates this behavior.  I use math and $scancounter to show that the stages I ran through each scan only execute once every 2 scans.

If you run the program, just turn on C11 to start the logic.  This is a much simplified logic, but demonstrates the same behavior I am seeing in my program.
You can look at the V2000-V2060 range to see it is always 2 scans between one execution and the next.  Based on what you posted, this must be a bug as it sounds like it should run through all stages every scan, rather than requiring them to be off for a full scan before being able to be turned on again.
« Last Edit: June 21, 2024, 11:11:29 AM by JeffS »

franji1

  • Bit Weenie
  • Host Moderator
  • Hero Member
  • *****
  • Posts: 3827
    • Host Engineering
Re: Stage Logic
« Reply #3 on: June 21, 2024, 01:04:38 PM »
Yes, there has to be 1 logic scan of "termination" behavior when a stage becomes disabled.

Some instructions have "termination" logic that gets ran whenever its encompassing stage (or even code block) terminates.  This behavior is done in the "next" PLC scan.  That is the behavior you are seeing.

So whenever a stage becomes disabled, the soonest it can begin executing its containing logic will be 2 scans from the current one.  The "termination" scan will be the next scan, and then if it is re-enabled it will start "normal" execution 2 scans from the current one.