Host Engineering Forum
General Category => Do-more CPUs and Do-more Designer Software => Topic started by: Andrew S on June 18, 2019, 04:38:06 PM
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Hi. I'm struggling with a facet of stage programming and I could use some assistance please.
The docs for stage programming say "All output coils used in a stage will be automatically turned off on the scan immediately following the scan in which the Jump to Stage and Jump to Multiple Stages (SGDIVRG) instructions are executed". With this being the case, how do I set bits in a stage, and then use them in a later stage if they're just going to be switched off when I leave the stage in which they're set?
[Insert confused emoticon here...]
Andrew.
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You can use them as OUTs in as many stages as you want. If you jump back from a later stage to earlier, and both have OUTs to the same element, it will glitch the output for one scan, but as long as jumps are forward, it will not.
Alternatively, you can use SET and RST, which are not automatically shut off.
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Gotcha. Thanks Bob.
Am I right in assuming that success/fail bits from async processes are treated as SET commands and therefore don't get reset across stage changes?
Andrew.
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Gotcha. Thanks Bob.
Am I right in assuming that success/fail bits from async processes are treated as SET commands and therefore don't get reset across stage changes?
Andrew.
Correct.