Host Engineering Forum
General Category => Do-more CPUs and Do-more Designer Software => Topic started by: Tark on November 13, 2015, 03:19:56 PM
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I just want to verify that if I have multiple RX/WX's that are Edge Triggered, if on Scan A they are all true, then they will all execute regardless of what the rung status is on Scan B? In other words, if I have 10 WX's that are triggered from the same bit, if on Scan A the bit is true all 10 of the WX's will execute even if on the next Scan the bit is false?
I'm assuming the above answer is Yes, then my next question will be - What happens in a case where a WX instruction is true on one scan, false on the next scan, then true, then false, would this build up a large que of the WX instruction?
Last question ;) - Do the DLRX/DLWX and MRX/MWX instructions perform in the same manner as the RX/WX instructions?
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I just want to verify that if I have multiple RX/WX's that are Edge Triggered, if on Scan A they are all true, then they will all execute regardless of what the rung status is on Scan B? In other words, if I have 10 WX's that are triggered from the same bit, if on Scan A the bit is true all 10 of the WX's will execute even if on the next Scan the bit is false?
I'm assuming the above answer is Yes, then my next question will be - What happens in a case where a WX instruction is true on one scan, false on the next scan, then true, then false, would this build up a large que of the WX instruction?
Last question ;) - Do the DLRX/DLWX and MRX/MWX instructions perform in the same manner as the RX/WX instructions?
Edges are latched in the instruction. Single events aren't missed, but multiples are not queued.
DLRX/WX and MRX/WX do work the same way.